1. Technical Field
This invention relates generally to processing transactions within a pipeline, and more particularly to correcting errors within such transactions.
2. Description of the Prior Art
Pipelining is a technique that is used to speed up the processing of transactions. Transactions include read commands, which read data from memory, and write commands, which write data to memory. Typically, only one transaction can be processed at a time. Inserting register points within transaction-processing logic is referred to as pipelining. The logic between two sets of register points is referred to as a pipeline stage. Pipelining allows a different transaction to be within each stage of the pipeline, thus increasing processing throughput. Pipelining also allows the frequency of the processor to be increased, because the levels of processing logic between register points are reduced. However, the overall time to process a transaction may be increased only slightly, due to the delay of the registers that are inserted in the logic. Pipelining also can increase complexity if there are dependencies between transactions.
If errors are detected within the pipeline, they usually are corrected in-line, within the pipeline stage where they occur, before the transactions can be properly processed and the resulting actions performed. An implementation for error correction may include additional hardware circuitry to correct the error when and where it is detected. However, such an implementation adds latency to the processing of both transactions with errors and transactions without errors. For this and other reasons, therefore, there is a need for the present invention.